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[VHDL-FPGA-Verilog] 基于CPLD的VHDL语言数字钟（含秒表）设计

Description: 基于CPLD的VHDL语言数字钟（含秒表）设计
Platform: | Size: 116224 | Author: gaojianlin19880605@163.com | Hits:

[VHDL-FPGA-Verilog] CPLD任意分频输出 VHDL

Description: CPLD任意分频输出 VHDL,调试通过
Platform: | Size: 666 | Author: spring718@163.com | Hits:

[VHDL-FPGA-Verilog] hdb3 decoder

Description: 我上期做的VHDL设计方案，用于在FPGA或CPLD中实现HDB3的编码-I do view on the VHDL design options for the CPLD or FPGA to achieve HDB3 code
Platform: | Size: 119808 | Author: 王薇 | Hits:

[VHDL-FPGA-Verilog] mcs_51_cpld

Description: 程序主要用硬件描述语言（VHDL）实现： 单片机与FPGA接口通信的问题-procedures major hardware description language (VHDL) to achieve : MCU and FPGA interface communication problems
Platform: | Size: 150528 | Author: 刘赛 | Hits:

[File Format] 基于VHDL与CPLD器件的FIR数字滤波器的设计

Description: 这是我看到的一些资料，希望与大家分享。也许这对您用处不大，但是我的一份诚意。-this is that I see some of the information and hope to share with you all. This may be less useful to you, but my sincerity.
Platform: | Size: 102400 | Author: yin | Hits:

[VHDL-FPGA-Verilog] primetime

Description: 这是ＶＨＤＬ语言编写的延时测试程序，用来测定ＣＰＬＤ的性能指标-This is the VHDL language delay the test procedure used to determine the performance CPLD
Platform: | Size: 52224 | Author: 张国梁 | Hits:

[ARM-PowerPC-ColdFire-MIPS] jtag_cpld_vhdl

Description: JTAG CPLD实现源代码，比用简单并口调试器快5倍以上。 以前总觉得简单的并口jtag板速度太慢，特别是调试bootloader的时候，简直难以忍受。最近没什么事情，于是补习了几天vhdl，用cpld实现了一个快速的jtag转换板。cpld用epm7128stc100-15，晶振20兆，tck频率5兆。用sjf2410作测试，以前写50k的文件用时5分钟，现在则是50秒左右。tck的频率还可以加倍，但是不太稳定，而且速度的瓶颈已经不在tck这里，而在通讯上面了。 -JTAG CPLD source code than the simple parallel debugger five times faster. Before feel simple parallel port JTAG board is too slow, especially when debugging Bootloader, simply intolerable. No matter recently, so VHDL tutorial for a few days, with cpld to achieve a rapid conversion of JTAG board. Cpld with epm7128stc100-15, 20 Katherine crystal, the frequency tck 5 trillion. Sjf2410 used for testing, before the document was made with 50k at 5 minutes, now it is about 50 seconds. Tck frequencies can also doubled, but not too stable, but the rate has not tck bottleneck here, and in the above communications.
Platform: | Size: 2048 | Author: 李伟 | Hits:

[VHDL-FPGA-Verilog] 100Examples

Description: 有关于VHDL举例,FPGA/CPLD的运用方面的例子-for example VHDL, FPGA/CPLD to the use of the example
Platform: | Size: 198656 | Author: 许宏亮 | Hits:

[Windows Develop] VHDLgdewrrrrrrrrrrrr

Description: 本设计中选用目前应用较广泛的VHDL硬件电路描述语言，实现对路口交通灯系统的控制器的硬件电路描述，通过编译、仿真，并下载到CPLD器件上进行编程制作，实现交通灯系统的控制过程。EDA技术是用于电子产品设计中比较先进的技术，可以代替设计者完成电子系统设计中的大部分工作，而且可以直接从程序中修改错误及系统功能而不需要硬件电路的支持，既缩短了研发周期，又大大节约了成本，受到了电子工程师的青睐。实现路口交通灯系统的控制方法很多，可以用标准逻辑器件、可编程序控制器PLC、单片机等方案来实现。但是这些控制方法的功能修改及调试都需要硬件电路的支持，在一定程度上增加了功能修改及系统调试的困难。因此，在设计中采用EDA技术，应用目前广泛应用的VHDL硬件电路描述语言，实现交通灯系统控制器的设计，利用MAXPLUSⅡ集成开发环境进行综合、仿真，并下载到CPLD可编程逻辑器件中，完成系统的控制作用。-the current design was chosen over a wide range of VHDL hardware description language circuit. Implementation of traffic lights at the junction of the controller hardware circuit description, compiler, simulation, to download and CPLD programming on production, traffic signal system to achieve the control process. EDA technology is used to design electronic products more advanced technology, designers can replace the complete electronic system design most of the work, but can directly from the process to amend the mistakes and system functions without the need for hardware circuits of support, both to shorten the development cycle, another significant cost savings by the electronic engineers of all ages. Achieving junction traffic signal system control many ways, using standard logic devic
Platform: | Size: 4096 | Author: jazvy | Hits:

[VHDL-FPGA-Verilog] EDAchuzuchejijia

Description: 在本示例程序中，用VHDL语言实现了出租车的记价功能，在Maxplus2环境下编写，可通过cpld下载板来验证程序。在压缩包中附有示例的目的，方法和仿真时序图，是学习VHDL好例子。-in this sample program, using VHDL of the entry price of a taxi function, in preparation FLEX10K environment, through cpld download plate to the verification process. The compression package with the purpose of example, the simulation methods and timing diagrams, is a good example to learn VHDL.
Platform: | Size: 339968 | Author: bkd | Hits:

[VHDL-FPGA-Verilog] CPLD_CCD

Description: 实现基于CPLD的CCD采集系统设计源码-based CPLD CCD Acquisition System Design FOSS
Platform: | Size: 66560 | Author: 周宇 | Hits:

[J2ME] CPLDheVHDLshuzisheji

Description: 数字设计——CPLD应用与VHDL源文件，很不错的，希望能对大家有用-digital design-- CPLD applications with the VHDL source files, very good, we hope to useful right
Platform: | Size: 107520 | Author: weilong1222 | Hits:

[VHDL-FPGA-Verilog] lcdexample

Description: cpld实现与液晶屏并口通信，VHDL 语言编程。对VHDL初学者应该有帮助的。-cpld achieve parallel with the LCD screen communications, VHDL programming. Right VHDL beginners should help.
Platform: | Size: 1024 | Author: 黄小光 | Hits:

[VHDL-FPGA-Verilog] jiaotongdeng

Description: 一个用VHDL编写的在CPLD上实现模拟交通灯的程序源代码-a VHDL prepared by the CPLD on the analog signal source code
Platform: | Size: 394240 | Author: 田冰 | Hits:

[VHDL-FPGA-Verilog] SS7160.ZIP

Description: 该代码为配合7号信令模块MK50H27的cpld(xilinx 95144)的逻辑代码,其中包括了VHDL及原理图.-the code to meet on the 7th of signaling modules MK50H27 cpld (Xilinx 95144 ) logic code, which included a schematic and VHDL.
Platform: | Size: 720896 | Author: 王珏 | Hits:

[Internet-Network] eathnet

Description: 百兆以太网mac和mii的vhdl源程，作IPcore的时候非常有用-Fast Ethernet MII and the VHDL source way for IPcore very useful when
Platform: | Size: 123904 | Author: 王前 | Hits:

[VHDL-FPGA-Verilog] VHDL_Development_Board_Sources

Description: 这是我最近买的一套CPLD开发板VHDL源程序并附上开发板的原理图,希望对你是一个很好的帮助!其中内容为:8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟.-which I have recently bought a CPLD Development Board VHDL source code accompanied the development of the plate diagram, You hope to be a good help! which states : eight priority encoder, multipliers, multi-path selectors, BCD binary switch, adder, subtraction device, the simple state machine, four comparators, seven of the digital control, i2c bus, lcd LCD allocated code switches, serial port, the buzzer sounded, matrix keyboards, Bomadeng, traffic lights, Digital Clock.
Platform: | Size: 4642816 | Author: Jawen | Hits:

[VHDL-FPGA-Verilog] CpldandEepromI2c

Description: verilog 编写的I2c协议程序，用于cpld读写EEPROM-verilog I2c agreement prepared by the procedures for cpld writable EEPROM
Platform: | Size: 447488 | Author: 丁明 | Hits:

[Software Engineering] verilog50%

Description: 本文主要介绍了50％占空比三分频器的三种设计方法，并给出了图形设计、VHDL设计、编译结果和仿真结果。设计中采用EPM7064AETC44-7 CPLD，在QUARTUSⅡ4.2软件平台上进行。 -This paper introduces a 50% duty cycle three dividers of the three design methods, and gives the graphic design, VHDL design, compile results and the simulation results. Design used EPM7064AETC44-7 CPLD. In QUARTUS II 4.2 software platform.
Platform: | Size: 187392 | Author: li | Hits:

[Other resource] 2006441156

Description: 有关VHDL的大量例程，对学习VHDL编程的人具有很大的帮助，不可不看.. -the large number of routines, VHDL, VHDL programming for the study of great help, can not do ..
Platform: | Size: 7667712 | Author: 陶生 | Hits:
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